Full Wafer Level Test

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Full Wafer Level Test
 

FWLT is a probing technique that tests an entire silicon wafer at once (one touch down) allowing reductions in test time and cost.

Our FWLT Probe Card features a controlled CTE (Coefficient of Thermal Expansion) probe head housing (developed in-house) to operate under a wide temperature range, utilizing our fine pitch, compliant vertical probe pin.

 


Related Link

NHK Web Link:      http://www.nhkspg.co.jp/eng/mc/index.html